1 ? fn2907.5 ha-5135 2.5mhz, precision op erational amplifier the intersil ha-5135 is a precision operational amplifier manufactured using a combination of key technological advancements to provide outst anding input characteristics. a super beta input stage is combined with laser trimming, dielectric isolation and matching techniques to produce 75 v (maximum) input offset voltage and 0.4 v/ o c input offset voltage average drift. ot her features enhanced by this process include 9nv/ hz (typ) input noise voltage, 1na input bias current and 140db open loop gain. these features coupled with 120db cmrr and psrr make the ha-5135 an ideal device for precision dc instrumentation amplifiers. excellent input char acteristics in conjunction with 2.5mhz bandwidth and 0.8v/ s slew rate, make this amplifier extremely useful for precision integrator and biomedical amplifier designs. this amplifier is also well suited for precision data acquisition and for accurate threshold detector applications. ha-5135 offers added features over the industry standard op-07 in regards to bandwidth and slew rate specifications. for the military grade product, refer to the ha-5135/883 data sheet. pinout ha-5135 (cerdip) top view note: both bal 1 pins are c onnected together internally. features ? low offset voltage. . . . . . . . . . . . . . . . . . . . . 75 v (max) ? low offset voltage drift . . . . . . . . . . . . . . . . . . . 0.4 v/ o c ? low noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9nv/ hz ? open loop gain. . . . . . . . . . . . . . . . . . . . . . . . . . . 140db ? unity gain bandwidth. . . . . . . . . . . . . . . . . . . . . . 2.5mhz ? all bipolar construction applications ? high gain instrumentation ? precision data acquisition ? precision integrators ? biomedical amplifiers ? precision threshold detectors 1 2 3 4 8 7 6 5 v+ out bal v- + bal 1 bal 1 -in +in - part number information part number temp. range ( o c) package pkg. no. HA7-5135-5 0 to 75 8 ld cerdip f8.3a data sheet january 2004 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2004. all rights reserved all other trademarks mentioned are the property of their respective owners. o b s o l e t e p r o d u ct no r e c o m m e nd e d r e p l a c e m e n t c o n t a c t o u r t e c h n i c a l s u p p o r t c e n t e r a t 1 - 8 8 8 - i n t e rs i l o r w w w . i n t e r s i l . c o m / t s c
2 absolute maximum rati ngs thermal information voltage between v+ and v- terminals . . . . . . . . . . . . . . . . . . . 40v differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7v output short circuit duration. . . . . . . . . . . . . . . . . . . . . . . indefinite operating conditions temperature ranges ha-5135-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to 75 o c thermal resistance (typical, note 2) ja ( o c/w) jc ( o c/w) cerdip package. . . . . . . . . . . . . . . . . 115 28 maximum junction temperature (note 1) . . . . . . . . . . . . . . . . 175 o c maximum storage temperature range . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300 o c caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. maximum power dissipation, including output load, must be designed to maintain the maximum junction temperature below 175 o c. 2. ja is measured with the component mount ed on an evaluation pc board in free air. electrical specifications v supply = 15v parameter test conditions temp. ( o c) ha-5135-5 units min typ max input characteristics offset voltage 25 - 10 75 v full - 50 130 v average offset voltage drift full - 0.4 1.3 v/ o c bias current 25 - 1 4na full - - 6na bias current average drift full - 0.02 0.04 na/ o c offset current 25 - - 4 na full - - 5.5 na offset current average drift full - 0.02 0.04 na/ o c common mode range full 12 - - v differential input resistance 25 20 30 - m ? input noise voltage (note 3) 0.1hz to 10hz 25 - - 0.6 v p-p input noise voltage density (note 3) f = 10hz 25 - 13.0 18.0 nv/ hz f = 100hz - 10.0 13.0 nv/ hz f = 1000hz - 9.0 11.0 nv/ hz input noise current (note 3) 0.1hz to 10hz 25 - 15 30 pa p-p input noise current density (note 3) f = 10hz 25 - 0.4 0.8 pa/ hz f = 100hz - 0.17 0.23 pa/ hz f = 1000hz - 0.14 0.17 pa/ hz transfer characteristics large signal voltage gain v out = 10v, r l = 2k ? 25 120 140 - db full 120 - - db common mode rejection ratio v cm = 10v full 106 120 - db closed loop bandwidth a vcl = +1 25 0.6 2.5 - mhz output characteristics output voltage swing r l = 600 ? 25 10 12 - v full 10 - - v ha-5135
3 full power bandwidth (note 4) r l = 2k ? 25 8 10 - khz output current v out = 10v 25 15 20 - ma output resistance note 5 25 - 45 - ? transient response (note 6) rise time 25 - 340 - ns slew rate 25 0.5 0.8 - v/ s settling time (note 7) 25 - 11 - s power supply characteristics supply current full - 1.0 1.7 ma power supply rejection ratio v s = 5v to 20v full 94 130 - db notes: 3. not tested. 90% of units meet or exceed these specifications. 4. full power bandwidth guaranteed based on slew rate measurement using: . 5. output resistance measured under open loop conditions (f = 100hz). 6. refer to test circuits section of the data sheet. 7. settling time is measured to 0.1% of final value for a 10v output step and a v = -1. electrical specifications v supply = 15v (continued) parameter test conditions temp. ( o c) ha-5135-5 units min typ max fpbw slew rate 2 v peak ------------------------------ - = test circuits and waveforms figure 1. slew rate and transie nt response test circuit small signal response large signal response in 100pf out 2k ? + - output input 0v 0v vertical scale: input = 50mv/div. output = 100mv/div. horizontal scale: 1 s/div. output input 0v 0v vertical scale: 5v/div. horizontal scale: 5 s/div. ha-5135
4 schematic diagram figure 2. settling time circuit test circuits and waveforms (continued) + - a.u.t. +15v -15v 2k ? 100pf v out 5k ? 5k ? 2k ? v in 2k ? to oscilloscope 2n4416 +15v notes: 8. a v = -1. 9. feedback and summing resistors should be 0.1% matched. 10. clipping diodes are optional. hp5082-2810 recommended. r 9 q 35 q 22 balance r 11 q 56 r 7 q 55 q 19 q 21 c 3 q 8 q 17 q 20 r 6 q 57 r 12 q 37 c 2 r 8 q 36 q 38 q 40 q 39 q 28 q 27 q 24 c 4 c 1 q 14 q 12 q 2 q 4 q 15 q 16 q 9 q 10 q 6 q 5 q 11 q 13 q 1 q 3 r 3 (-) inverting input q 52 q 7 q 53 r p18 q 46 r 19 q 48 q 50 q 41 q 49 z 1 r 13 r 20 r 14 r 2 r 17 q 25 q 26 q 42 q 51 q 31 (+) non- input inverting q 45 q 34 q 30 r 15 out r 16 q 33 q 47 q 32 q 43 q 58 q 44 v+ v- q 54 q 18 r 4 r 10 r 5 ha-5135
5 application information power supply decoupling although not absolutely necessary, it is recommended that all power supply lines be decoupled with 0.01 f ceramic capacitors to ground. decoupling capacitors should be located as near to the amplifier terminals as possible. considerations for prototyping: the following list of recommendations are suggested for prototyping. 1. resolving low level signals requires minimizing leakage currents caused by external circuitry. use of quality insulating materials, thorough cleaning of insulating surfaces and implementation of moisture barriers when required is suggested. 2. error voltages generated by thermocouples formed between dissimilar metals in the presence of temperature gradients should be minimized. isolation of low level circuity from heat generating components is recommended. 3. shielded cable input leads, guard rings and shield drivers are recommended for the most critical applications. large capacitive loads when driving large capacitive loads (>500pf), a small value resistor ( 50 ? ) should be connected in series with the output and inside the feedback loop. offset voltage adjustment (see figure 3) a 20k ? balance potentiometer is recommended if offset nulling is required. however, other potentiometer values such as 10k ? , 50k ? and 100k ? may be used. the minimum adjustment range for given values is 2mv. v os tc of the amplifier is optimized at minimal v os . tested offset adjustment is |v os + 1mv| minimum referred to output. saturation recovery input and output saturation recovery time is negligible in most applications. however, care should be exercised to avoid exceeding the absolut e maximum ratings of the device. differential input voltages inputs are shunted wit h back-to-back diodes for overvoltage protection. in applications wher e differential input voltages in excess of 1v are applied between the inputs, the use of limiting resistors at the inputs is recommended. typical applications the excellent input and gain characteristics of ha-5135 are well suited for precision inte grator applications. accurate integration over seven decades of frequency using ha-5135, virtually nullifies the need for more expensive chopper-type amplifiers. low v os coupled with high open loop gain, high cmrr and high psrr make ha-5135 ideally suited for precision detector applications, such as the zero crossing detector shown in figure 5. 2 6 1 7 8 v+ + 4 3 5 r p (note) 20k ? optional connection - figure 3. offset nulling connections 2 1 7 8 + 4 3 5 r b c 6 r out - figure 4. precision integrator ha-5135
6 figure 5. zero crossing detector figure 6. precision instrumentation amplifier 2 1 7 8 + 4 3 5 6 out r in input optional for output swing limiting output 13v 200 s/div. input 5mv 200 s/div. r f - 4.5k ? 500 ? 4.5k ? ha-5135 -15v +15v 2k ? 2k ? 2k ? ha-5135 +15v 2k ? -15v ha-5135 note: a v = 100 + - + - + - typical performance curves figure 7. input offset voltage, input bias and offset current vs temperature figure 8. input bias current vs differential input voltage 80 70 60 50 40 -80 40 160 temperature ( o c) input offset voltage ( v) input bias current 30 20 10 120 80 -40 0 input offset current typical 0 4 3 2 1 0 4 2 0 -4 -2 input offset current ( na ) input bias current ( na ) |v os | 6 4 2 -10 -4 -2 differential input voltage (v) bias current (na) 0 -8 -6 10 4 28 6 0 -2 -4 -6 ha-5135
7 figure 9. ha-5135 offset voltage stability vs time figure 10. input noise vs frequency figure 11. open loop frequency response f igure 12. closed loop frequency response figure 13. small signal bandwidth and phase margin vs load capacitance figure 14. output voltage swing vs frequency typical performance curves (continued) 10 5 0 -5 -10 26 30 time (days) total drift with time ( v) v supply = 15v 20 4 t c = 1 o c, a v = 1000 measurement and environmental systems allowed 12 hour stabilization period 810 40 frequency (hz) 14 12 10 input noise voltage (nv/ hz ) 10 10k 100 1k noise voltage noise current 8 6 4 2 0 1.4 1.2 1.0 input noise current (pa/ hz ) 0.8 0.6 0.4 0.2 0 100k frequency (hz) 100k 10m 1k 100 10 160 140 120 100 -20 0 20 40 60 80 phase angle gain 1 10k 1m open loop voltage gain (db) 0 45 90 135 180 phase (degrees) frequency (hz) closed loop gain (db) 80 0 10 20 30 40 50 60 70 -10 100k 10m 1k 100 10 1 10k 1m load capacitance (pf) 10,000 100 10 phase margin (degrees) 60 1000 phase margin bandwidth 50 40 30 20 10 0 2.6 2.5 2.4 2.35 unity gain bandwidth (mhz) output voltage swing (v p-p ) 10 20 35 r l = 2k ? v supply = 20v 25 15 5 30 v supply = 15v v supply = 10v v supply = 5v frequency (hz) 100k 1k 100 10k 1m ha-5135
8 figure 15. maximum output voltage swing vs load resistance figure 16. normalized ac parameters vs supply voltage figure 17. cmrr vs frequency figure 18. psrr vs frequency figure 19. settling time for various output step voltages figure 20. power supply current vs temperature typical performance curves (continued) 30 25 20 15 10 1 100 10k load resistance ( ? ) 5 1k 10 output voltage swing (v p-p ) v supply = 15v v supply = 10v v supply = 5v 0 1.1 1.0 0.9 0.8 2161820 supply voltage ( v) normalized ac parameters 46 8 101214 0.7 0.6 0 bandwidth slew rate referred to value at 15v 140 120 100 80 60 40 20 0 cmrr (db) frequency (hz) 10 10k 100 1k 100k 1 frequency (hz) psrr (db) 10 10k 100 1k 100k 1 140 120 100 80 60 40 20 0 settling time ( s) 02468 -10 -5 0 5 10 10 12 14 16 to 10mv to 1mv output voltage step - volts from 0 volts to 10mv to 1mv v s = 20v temperature ( o c) supply current (ma) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -80 40 160 120 80 -40 0 v s = 15v v s = 10v v s = 5v ha-5135
9 die characteristics die dimensions: 72 mils x 103 mils x 19 mils (1840 m x 2620 m x 483 m) metallization: type: al, 1% cu thickness: 16k ? 2k ? substrate potential (powered up): v- passivation: type: nitride (si 3 n 4 ) over silox (sio 2 , 5% phos.) silox thickness: 12k ? 2k ? nitride thickness: 3.5k ? 1.5k ? transistor count: 71 process: bipolar dielectric isolation metallization mask layout ha-5135o bal1 v+ out bal1 v- +in -in bal2 ha-5135
10 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that da ta sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com ha-5135 ceramic dual-in-line fr it seal packages (cerdip) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. 2. the maximum limits of lead di mensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this co nfiguration dimension b3 replaces dimension b2. 5. this dimension allows for off- center lid, meniscus, and glass overrun. 6. dimension q shall be measured from the seating plane to the base plane. 7. measure dimension s1 at all four corners. 8. n is the maximum number of terminal positions. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch bbb c a - b s c q l a seating base d plane plane -d- -a- -c- -b- d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 a m s s ccc c a - b m d s s aaa ca - b m d s s e a f8.3a mil-std-1835 gdip1-t8 (d-4, configuration a) 8 lead ceramic dual-in-line frit seal package symbol inches millimeters notes min max min max a - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 0.405 - 10.29 5 e 0.220 0.310 5.59 7.87 5 e 0.100 bsc 2.54 bsc - ea 0.300 bsc 7.62 bsc - ea/2 0.150 bsc 3.81 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.060 0.38 1.52 6 s1 0.005 - 0.13 - 7 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2, 3 n8 88 rev. 0 4/94
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